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Description: VHDL实现CISC模型微处理器设计（含有rom和ram）本程序实现的是输入10个数，输出最小负数-VHDL model to achieve CISC microprocessor design (with rom and ram) to achieve this procedure is the number of input 10 and output the smallest negative
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Size: 1807360 |
Author: 叶才三 |
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Description: DS12CR887实时时钟芯片功能丰富，其正常工作电压为3.3 V，工作电压范围为2.97 V～3.63 V，是应用在DSP硬件电路中的理想时钟芯片。DSl2CR887的具体的特性如下：
(1) 具有10字节RAM用来存储时间信息。能够自动产生年、月、日、时、分、秒、星期等时间信息，并且有时、分、秒的闹铃功能，温度25℃时每个月的时间误差在±1分钟以内。
(2) 内部自带电池，外部掉电时，温度25℃时其内部时间信息能够保持5年之久。
(3) 对于一天内的时间记录，有12小时制和24小时制两种模式。在12小时制模式中，用AM和PM区分上午和下午。
(4) 时间有二进制数和BCD码两种表示方法。
(5) 内置128字节RAM，其中10字节RAM用来存储时间信息，4字节RAM用来存储控制信息，称为控制寄存器，114字节的通用RAM可供用户使用。
(6) 用户还可对DS12C887进行编程
-DS12CR887 real-time clock chips, and the normal function of rich working voltage is 3.3 V, working voltage range as 2.97 V- a 3.63 V, is used in digital signal processor (DSP) hardware circuit of the ideal clock chip. The specific characteristics of DSl2CR887 are as follows:
(1) is used to store the RAM 10 bytes. Automatically generate year, month, day, week, minutes and seconds, such time information, and sometimes, minutes and seconds of alarm functions, while 25 degrees Celsius temperature per month during the time error within ± 1 minute.
(2) internal cabin batteries, external power, the internal temperature of 25 degrees Celsius can keep time information for 5 years.
(3) for the time of day, 12 hours and 24 hours of two kinds of patterns. In 12 hours system model, AM and PM distinction in the morning and afternoon.
(4) time is binary number and BCD two methods.
Built-in 128 bytes (5), including 10 bytes RAM is used to store information, RAM four bytes RAM time is us
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Size: 72704 |
Author: ChenSheng |
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Description: 根据摄像机透视投影模型, 通过提取特征点进行摄像机的运动估计, 提出一种基于FMA的补偿方法Z该方法针对图像连续帧间晃动幅度较大的情况, 通过均值滤波合成当前帧及其前几帧的运
动进行补偿。-A mo t ion model is p resen ted to est im ate the mo t ion param eters fo r im age stab ilizat ion
by t rack ing featu re po in t s f rom con secu t ive f ram es. A f ram e2to2mo saic algo rithm (FMA ) fo rmo2
t ion compen sat ion is described. The p ropo sed algo rithm is ab le to compen sate the mo t ion by fu s2
ing the mo t ion of the cu rren t f ram e w ith that of the p reviou s f ram es. Experim en tal resu lt s show
it s effect ive and po ten t ial app licat ion s
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Size: 301056 |
Author: 尹钊 |
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Description: RT12864M 汉字图形点阵液晶显示模块，可显示汉字及图形，内置8192 个中文汉字（16X16 点阵）、128 个字符（8X16
点阵）及64X256 点阵显示RAM（GDRAM）。-For additional RT12864M Cha of Shiwa Graphics, Liao owned by the Di TFT- dramaずmodel \" module Benanchituan the drama Cha For additional Shiwahu Mian graphical
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Size: 465920 |
Author: Keven_lee |
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Description: 基于CRF++-0.53的改良版，修正了模型输入时多行空行导致的线程错误，优化了多线程操作，除LBFGS无法优化外，其余迭代操作全部多线程化，66MB模型在16线程服务器上运行，内存占用5.35GB，CPU利用率一般100 ，只有运行LBFGS时为7 。仅支持64位Windows操作系统，使用VC2008编译，不支持32位操作系统或Linux（Windows线程模型）。-Optimized CRF++-0.53. Fixed multi-empty line input bug. Optimized multi-threaded operation. Only LBFGS is not optimized due to its complexity. A 66MB train model runs on a server with 16 threads consumes 5.35GB RAM and only when running LBFGS the CPU utilization is 7 , otherwise CPU utilization is 100 . 64bit Windows Operation ONLY. No support for 32bit Windows or Linux (Windows Thread Model).
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Size: 44032 |
Author: 吴岳 |
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Description: 谈谈我自己读这套书的心得。抛砖引玉。 首先要清楚这套书的定位：它是古典的算法分析的工具书。 1.古典（classic）体现在模型和问题上。 模型就是顺序算法（sequential algorithms）的经典模型。大名鼎鼎的MIX并非是个程序设计语言这么简单，而是一个计算模型：即标准指令集RAM。这是个非常经典，也是非常符合现实的上界（upper bounds）模型。 该书涉及到的问题是计算机科学诞生之初就自然面对-Talk about my own experiences reading this book. Start a discussion. First, to be clear positioning of this book: it is a classical algorithm analysis tool. 1. Classical (classic) embodied in the model and on the issue. Model is the classic model of sequential algorithms (sequential algorithms). The MIX famous is not simple as a programming language, but a calculation model: that is, the standard instruction set RAM. This is a very classic, is also very much in line with the reality of the upper bound (upper bounds) model. The book involves the natural face of the beginning of the birth of computer science
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Size: 27985920 |
Author: 陈炜东 |
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Description: Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
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Size: 9216 |
Author: 张昊溢 |
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Description: 此示例包括工作四功能的计算器
基于8051单片机的。该电路还演示了
行业标准的字母数字液晶显示模块，
与通用键盘模型。正如你所看到的，
后者可以模拟任何设计矩阵键盘
像你在乎吸引太多的现实主义。
同样有趣的是电路使用外部存储器的事实，
与8051和6264的RAM芯片之间的相互作用
模拟得出的。
两个8051和RAM芯片支持弹出窗口
可以选择从调试菜单一旦
调试会话正在进行。-This sample comprises a working four function calculator
based an 8051 microcontroller. The circuit also demonstrates
the industry standard alphanumeric LCD display model,
and the universal keypad model. As you can see,
the latter allows you to simulate any design of matrix keypad
with as much realism as you care to draw.
Also of interest is the fact the circuit uses external memory,
and the interaction between the 8051 and the 6264 RAM chip
is simulated as drawn.
Both the 8051 and the RAM chip support popup windows
which can be selected from the Debug menu once
a debugging session is under way.
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Size: 118784 |
Author: 张俊 |
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Description: 义隆单片机芯片资料，型号：EM78P224N,ROM容量：4K,RAM容量：176,8位单片机-Elan microcontroller chip data, model: EM78P224N, ROM capacity: 4K, RAM capacity: 176,8 bit microcontroller
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Size: 995328 |
Author: zhangtao |
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Description: 液晶驱动芯片，型号PCF8576，显示内容：20*8，显示RAM:40*4，-LCD driver chip, model PCF8576, display: 20* 8, display RAM: 40* 4,
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Size: 173056 |
Author: zhangtao |
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Description: 双口RAM 的乒乓存储结构（芯片型号CY7C09279）
应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging has verified]
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Size: 1024 |
Author: 61408520 |
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Description: msp430f6779 DMA的功能使用-// Description: A 16 word block from 1FC0-1FDFh is transfered to 1FE0h-1FFFh
// using DMA0 in a burst block using software DMAREQ trigger.
// After each transfer, source, destination and DMA size are
// reset to initial software setting because DMA transfer mode 5 is used.
// P1.0 is toggled during DMA transfer only for demonstration purposes.
// ** RAM location 0x1C00- 0x1C3F used- make sure no compiler conflict**
// ACLK = REFO = 32kHz, MCLK = SMCLK = default DCO 1048576Hz
// Use large memory model
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Size: 2048 |
Author: zxb |
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